Memory read operation in all kinds of sense amplifiers is achieved by comparing input data with a reference signal to determine the logic state of the input data. Conventional differential sense amplifiers, which are used in memory devices such as standard Dynamic Random Access Memory (DRAM) devices, are connected to two bit lines, one bit line providing the data to be read while the other bit line is used for reference voltage generation.
In contrast to that, single-ended sense amplifiers, which are used in memory devices such as embedded or special Dynamic Random Access Memory (DRAM) devices, are coupled to a single bit line only.
A particular style of single-ended sense amplifier employs a sense amplifier with two input/output nodes, one of which is coupled to an input data line (bit line), and the other is used to feed in a reference signal required for the read operation process. FIG. 1 shows an example of such a single-ended sense amplifier which has been proposed by the Applicant and previously described in publication EP 2 365 487 A2. It comprises two branches, each having a PMOS transistor and a NMOS transistor connected in series, arranged in a way that they form cross-coupled inverters. The transistors are double gate transistors having a first control gate and a second control gate that can be independently operated. The first branch comprises PMOS transistor T4 in series with NMOS transistor T3 in between power supplies V4 and V3, while the second branch comprises PMOS transistor T1 in series with NMOS transistor T2 in between power supplies V1 and V2. The first gates of transistors T1 and T2 are connected together (input of the inverter formed by the second branch) and connected to the middle node between transistors T3 and T4 (output of the inverter formed by the first branch), thereby forming a first input/output node N1 of the sense amplifier which is used to feed in a reference signal REF. The first gates of transistors T4 and T3 are connected together (input of the inverter formed by the first branch) and to the middle node between transistors T1 and T2 (output of the inverter formed by the second branch), thereby forming a second input/output node N2 of the sense amplifier which is coupled to a bit line BL. The second gates of transistors T1, T2, T3 and T4 are denoted BG1, BG2, BG3 and BG4 and are herein referred to as back control gates. Such back control gates are used to modulate the first-gate-related threshold voltages of their respective transistors.
A problem arises from the fact that such a circuit is not necessarily symmetrical or, depending on the particular operation principle, is by purpose designed asymmetrically. Indeed both branches may have different designs concerning dimensions of the respective transistors (T1 being compared to T4, and T2 being compared to T3). Moreover, the first and second nodes N1, N2 may be operated in a different manner and with different loads (with nodes N1 and N2 being either both inputs or both outputs), and the operating points of all transistors may differ from each other during the sensing process (once again T1 is compared to T4, and T2 to T3). Note that these asymmetries usually apply to the operation of a single-ended sense amplifier. Thus, for ensuring proper operation of the circuit, widths and lengths of the transistors must be thoroughly chosen (and T1 and T4, respectively, T2 and T3, may intentionally differ). Reference, bias, and supply voltage must also be well defined and well controlled, too.
In practice however, all these parameters and the transistor properties (current drive capability, threshold voltage, transconductance, drain conductance, etc.) are prone to variations (PVT: process, voltage, temperature). As the single-ended sense amplifier is usually designed and operated as a non-symmetrical circuit, PVT variations do not compensate for each other in the two branches and malfunction of the circuit may result.
Generally speaking, this problem occurs in the case of any sense amplifier that does not rely on a fully-symmetrical differential circuit structure, and more specifically for sense amplifier circuits sensing a bitline against a reference voltage, i.e., against a non in-situ generated reference, which is not the case for sense amplifiers that generate their own references through shorting first and second bitlines in a precharge/equalizing phase or at least by precharging them to same potentials before a sense process is started.